View MC33910_4287052.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor Advance Information
Document Number: MC33910 Rev. 5.0, 12/2008
LIN System Basis Chip with High Side Drivers
The 33910 is a Serial Peripheral Interface (SPI) controlled System Basis Chip (SBC), combining many frequently used functions in an MCU based system, plus a Local Interconnect Network (LIN) transceiver. The 33910 has a 5.0 V, 50 mA low dropout regulator with full protection and reporting features. The device provides full SPI readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN Protocol Specification 2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry that can be disabled for higher data rates. Two 50 mA high side switches with optional pulse-width modulated (PWM) are implemented to drive small loads. One high voltage input is available for use in contact monitoring, or as external wake-up input. This input can be used as high voltage Analog Input. The voltage on this pin is divided by a selectable ratio and available via an analog multiplexer. The 33910 has three main operating modes: Normal (all functions available), Sleep (VDD off, wake-up via LIN, wake-up inputs (L1), cyclic sense and forced wake-up), and Stop (VDD on with limited current capability, wake-up via CS, LIN bus, wake-up inputs, cyclic sense, forced wake-up and external reset). The 33910 is compatible with LIN Protocol Specification 2.0, 2.1, and SAEJ2602-2. Features * * * * * * * *
Device Full-duplex SPI interface at frequencies up to 4.0 MHz LIN transceiver capable of up to 100 kbps with wave shaping MC33910G5AC/R2 Two 50 mA high side switches One high voltage analog/logic Input MC34910G5AC/R2 Configurable window watchdog 5.0 V low drop regulator with fault detection and low voltage reset (LVR) circuitry Switched/protected 5.0 V output (used for Hall sensors) Pb-free packaging designated by suffix code AC
33910
VBAT
VS1 VS2 VSENSE HS1 L1
33910
SYSTEM BASIS CHIP WITH LIN 2ND GENERATION
AC SUFFIX (Pb-FREE) 98ASH70029A 32-PIN LQFP
ORDERING INFORMATION
Temperature Range (TA) - 40C to 125C 32-LQFP -40C to 85C Package
VDD PWMIN ADOUT0
LIN
LIN INTERFACE
MCU
MOSI MISO SCLK CS RXD TXD IRQ RST
LGND PGND AGND
HVDD HS2 WDCONF
Figure 1. 33910 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. This specification support the following products
Device MC33910AC MC34910G5AC Temperature - 40 to 125C - 40 to 85C Generation 2.5 2.5 Specification Rev. 5.0(1) Rev. 5.0(1)
Notes 1. Changes to Rev. 5 include: - Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 test conditions) performance to achieve +/-6 kV min on the LIN pin - Immunity against ISO7637 pulse 3b - Reduce EMC emission level on LIN - Improve EMC immunity against RF - target new specification including 3x68 pF - Comply with J2602 conformance test
Table 2. This specification does not support the following products
Device MC33910BAC/R2 MC34910BAC/R2 Temperature - 40 to 125C - 40 to 85C Generation 2.0 2.0 Specification Rev 1.0 to 4.0(2) Rev 1.0 to 4.0(2)
Notes 2. For device specifications, refer to the documentation archive history. The current specification does not cover these products.
33910
2
Analog Integrated Circuit Device Data Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
RST IRQ
VS2
VS1
VDD
INTERNAL BUS
INTERRUPT CONTROL MODULE LVI, HVI, ALL OT (VDD, HS, LIN, SD)
AGND VOLTAGE REGULATOR PGND
RESET CONTROL MODULE LVR, WD, EXT C
5.0 V OUTPUT MODULE
HVDD
WINDOW WATCHDOG MODULE PWMIN HIGH SIDE CONTROL MODULE
VS2
VS2
HS1
MISO HS2 MOSI SCLK CS ADOUT0 SPI & CONTROL ANALOG MULTIPLEXER VBAT SENSE MODULE CHIP TEMPERATURE SENSE MODULE L1 ANALOG INPUT MODULE VSENSE
WAKE-UP MODULE
RXD TXD
DIGITAL INPUT MODULE
LIN PHYSICAL LAYER
LIN
LGND
WDCONF
Figure 2. 33910 Simplified Internal Block Diagram
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
AGND HVDD VDD VSENSE VS1 NC* VS2 26 HS1 25
29
31
30
RXD TXD MISO MOSI SCLK CS ADOUT0 PWMIN
1 2 3 4 5 6 7 8 * Special Configuration Recommended / Mandatory for Marked NC Pins
27
32
28
24 23 22 21 20 19 18 17
HS2 L1 NC* NC* NC* NC* PGND NC*
10 IRQ
11
12
13
14
15
16
RST
NC*
WDCONF
LGND
LIN
NC*
Figure 3. 33910 Pin Connections Table 3. 33910 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.
Pin 1 2 3 4 5 6 7 8 9 10 Pin Name RXD TXD MISO MOSI SCLK CS ADOUT0 PWMIN RST IRQ Formal Name Receiver Output Transmitter Input SPI Output SPI Input SPI Clock SPI Chip Select Analog Output Pin 0 PWM Input Internal Reset I/O Internal Interrupt Output Definition This pin is the receiver output of the LIN interface which reports the state of the bus voltage to the MCU interface. This pin is the transmitter input of the LIN interface which controls the state of the bus output. SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the high-impedance state. SPI (Serial Peripheral Interface) data input. SPI (Serial Peripheral Interface) clock Input. SPI (Serial Peripheral Interface) chip select input pin. CS is active low. Analog Multiplexer Output. High Side Pulse Width Modulation Input. Bidirectional Reset I/O pin - driven low when any internal reset source is asserted. RST is active low. Interrupt output pin, indicating wake-up events from Stop Mode or events from Normal and Normal request modes. IRQ is active low.
33910
NC*
9
4
Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
Table 3. 33910 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.
Pin 11, 15-17, 1922, 28 12 13 14 18 23 24 25 26 27 29 30 31 32 Pin Name NC WDCONF LIN LGND PGND L1 HS2 HS1 VS2 VS1 VSENSE HVDD VDD AGND Watchdog Configuration Pin LIN Bus LIN Ground Pin Power Ground Pin Wake-up Input Formal Name No connect This input pin is for configuration of the watchdog period and allows the disabling of the watchdog. This pin represents the single-wire bus transmitter and receiver. This pin is the device LIN ground connection. It is internally connected to the PGND pin. This pin is the device low side ground connection. It is internally connected to the LGND pin. This pin is the wake-up capable digital input(3). In addition, L1 input can be sensed analog via the analog multiplexer. High side switch outputs. These pins are device battery level power supply pins. VS2 is supplying the HSx drivers while VS1 supplies the remaining blocks.(4) Battery voltage sense input.(5) +5.0 V switchable supply output pin.(6) +5.0 V main voltage regulator output pin.(7) This pin is the device analog ground connection. Definition
High Side Outputs
Power Supply Pin Voltage Sense Pin Hall Sensor Supply Output Voltage Regulator Output Analog Ground Pin
Notes 3. When used as digital input, a series 33 k resistor must be used to protect against automotive transients. 4. Reverse battery protection series diodes must be used externally to protect the internal circuitry. 5. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It is strongly recommended to connect a 10 k resistor in series with this pin for protection purposes. 6. External capacitor (1.0 F < C < 10 F; 0.1 < ESR < 5.0 ) required. 7. External capacitor (2.0 F < C < 100 F; 0.1 < ESR < 10 ) required.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 4. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Supply Voltage at VS1 and VS2 Normal Operation (DC) Transient Conditions (load dump) Supply Voltage at VDD Input / Output Pins Voltage Interrupt Pin (IRQ)(9) HS1 and HS2 Pin Voltage (DC) L1 Pin Voltage Normal Operation with a series 33k resistor (DC) Transient input voltage with external component (according to ISO7637-2) (See Figure 5, page 19) VSENSE Pin Voltage (DC) LIN Pin Voltage Normal Operation (DC) Transient input voltage with external component (according to ISO7637-2) (See Figure 4, page 19) VDD Output Current VBUSDC VBUSTR IVDD -18 to 40 -150 to 100 VL1DC VL1TR VVSENSE -18 to 40 100
(8)
Symbol
Value
Unit
V VSUP(SS) VSUP(PK) VDD VIN VIN(IRQ) VHS -0.3 to 27 -0.3 to 40 -0.3 to 5.5 -0.3 to VDD +0.3 -0.3 to 11 - 0.3 to VSUP +0.3 V V V V
CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD, HVDD
-27 to 40
V V
Internally Limited
A
Notes 8. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device. 9. Extended voltage range for programming purpose only.
33910
6
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 4. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ESD Capability AECQ100 Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 ) LIN Pin L1 all other Pins Charge Device Model - JESD22/C101 (CZAP = 4.0 pF) Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32) All other Pins (Pins 2-7, 10-15, 18-23, 26-31) According to LIN Conformance Test Specification / LIN EMC Test Specification, August 2004 (CZAP = 150 pF, RZAP = 330 ) Contact Discharge, Unpowered LIN pin with 220 pF LIN pin without capacitor VS1/VS2 (100 nF to ground) L1 input (33 k serial resistor) According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 ) Unpowered LIN pin with 220 pF and without capacitor VS1/VS2 (100 nF to ground) L1 input (33 k serial resistor) THERMAL RATINGS Operating Ambient Temperature (10) 33910 34910 Operating Junction Temperature Storage Temperature Thermal Resistance, Junction to Ambient Natural Convection, Single Layer board (1s)(10), (11) Natural Convection, Four Layer board (2s2p)(10), (12) Thermal Resistance, Junction to Case(13) Peak Package Reflow Temperature During Reflow(14), (15) Notes 10. 11. 12. 13. 14. 15. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. RJC TPPRT TJ TSTG RJA 85 56 23 Note 15 C/W C TA -40 to 125 -40 to 85 -40 to 150 -55 to 150 C C C/W C VESD4-1 VESD4-2 VESD4-3 8000 8000 8000 VESD3-1 VESD3-2 VESD3-3 VESD3-4 20k 11k > 12k 6000 VESD2-1 VESD2-2 750 500 VESD1-1 VESD1-2 VESD1-3 8.0k 6.0k 2000 Symbol Value Unit V
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SUPPLY VOLTAGE RANGE (VS1, VS2) Nominal Operating Voltage Functional Operating Voltage(16) Load Dump SUPPLY CURRENT RANGE (VSUP = 13.5 V) Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(17) Stop Mode, VDD ON with IOUT = 100 A, LIN Recessive State (19) (20) , 5.5 V < VSUP < 12 V VSUP = 13.5 V 13.5 V < VSUP < 18 V Sleep Mode, VDD OFF, LIN Recessive State(17), (19) 5.5 V < VSUP < 12 V VSUP = 13.5 V 13.5 V VSUP < 18 V Cyclic Sense Supply Current Adder(21) SUPPLY UNDER/OVER-VOLTAGE DETECTIONS Power-On Reset (BATFAIL)(22) Threshold (measured on VS1)(21) Hysteresis (measured on VS1)(21) VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSOV VSOV_HYS 18 - 19.25 1.0 20.5 - VSUV VSUV_HYS 5.55 - 6.0 0.2 6.6 - VBATFAIL VBATFAIL_HYS 1.5 - 3.0 0.9 3.9 - V ICYCLIC ISLEEP - - - - 27 33 160 10 35 48 300 - A
(17), (18),
Symbol
Min
Typ
Max
Unit
VSUP VSUPOP VSUPLD
5.5 - -
- - -
18 27 40
V V V
IRUN ISTOP
-
4.5
10
mA A
- - -
47 62 180
80 90 400 A
V
V
Notes 16. Device is fully functional. All features are operating. 17. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled. 18. 19. 20. 21. 22. Total IDD current (including loads) below 100 A. Stop and Sleep Modes current will increase if VSUP exceeds13.5 V. This parameter is guaranteed after 90 ms. This parameter is guaranteed by process monitoring but not production tested. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.
33910
8
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic VOLTAGE REGULATOR
(23)
Symbol
Min
Typ
Max
Unit
(VDD) VDDRUN 4.75 IVDDRUN VDDDROP - VDDSTOP 4.75 IVDDSTOP LRRUN LRSTOP 6.0 5.0 13 5.25 36 mA mV - - - - 25 25 mV LDRUN LDSTOP TPRE 90 TPRE_HYS TSD TSD_HYS - 150 - 115 13 170 13 140 - 190 - C C C - - - - 80 50 C 0.1 0.25 V 60 5.00 110 5.25 200 mA V V
Normal Mode Output Voltage 1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation Dropout Voltage(24) IVDD = 50 mA Stop Mode Output Voltage IVDD < 5.0 mA Stop Mode Output Current Limitation Line Regulation Normal Mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA Stop Mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA Load Regulation Normal Mode, 1.0 mA < IVDD < 50 mA Stop Mode, 0.1 mA < IVDD < 5.0 mA Over-temperature Prewarning (Junction)(25)
Interrupt generated, VDDOT Bit Set Over-temperature Prewarning Hysteresis(25) Over-temperature Shutdown Temperature Over-temperature Shutdown Hysteresis (Junction)(25)
(25)
HALL SENSOR SUPPLY OUTPUT(26) (HVDD) VDD Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100% IHVDD = 15 mA Current Limitation Dropout Voltage IHVDD = 15 mA; IVDD = 5.0 mA Line Regulation IHVDD = 5.0 mA; IVDD = 5.0 mA Load Regulation 1.0 mA > IHVDD > 15 mA; IVDD = 5.0 mA Notes 23. Specification with external capacitor 2.0 F < C < 100 F and 100 m ESR 10 . 24. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V). 25. This parameter is guaranteed by process monitoring but not production tested. 26. Specification with external capacitor 1.0 F < C < 10 F and 100 m ESR 10 . LDHVDD - - 20 LRHVDD - - 40 mV IHVDD HVDDDROP - 160 300 mV HVDDACC -2.0 20 - 35 2.0 50 mA mV %
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic RST INPUT/OUTPUT PIN (RST) VDD Low Voltage Reset Threshold Low-state Output Voltage IOUT = 1.5 mA; 3.5 V VSUP 27 V High-state Output Current (0 V < VOUT < 3.5 V) Pull-down Current Limitation (internally limited) VOUT = VDD Low-state Input Voltage High-state Input Voltage MISO SPI OUTPUT PIN (MISO) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 A Tri-state Leakage Current 0 V VMISO VDD SPI INPUT PINS (MOSI, SCLK, CS) Low-state Input Voltage High-state Input Voltage MOSI, SCLK Input Current 0 V VIN VDD CS Pull-up Current 0 V < VIN < 3.5 V INTERRUPT OUTPUT PIN (IRQ) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 A Leakage Current VDD VOUT 10 V PULSE WIDTH MODULATION INPUT PIN (PWMIN) Low-state Input Voltage High-state Input Voltage Pull-up current 0 V < VIN < 3.5 V VIL VIH IPUPWMIN 10 20 30 -0.3 0.7 x VDD - - 0.3 x VDD VDD +0.3 V V A IOUT - - 2.0 VOH VDD -0.8 - VDD mA VOL 0.0 - 0.8 V V IPUCS 10 20 30 VIL VIH IIN -10 - 10 A -0.3 0.7 x VDD - - 0.3 x VDD VDD +0.3 V V A ITRIMISO -10 - 10 VOH VDD -0.9 - VDD A VOL 0.0 - 1.0 V V VIL VIH IOH IPD_MAX 1.5 -0.3 0.7 x VDD - - - 8.0 0.3 x VDD VDD +0.3 V V VRSTTH VOL 0.0 -150 - -250 0.9 -350 A mA 4.3 4.5 4.7 V V Symbol Min Typ Max Unit
33910
10
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic HIGH SIDE OUTPUTS HS1 AND HS2 PINS (HS1, HS2) Output Drain-to-Source On Resistance TJ = 25C, ILOAD = 50 mA; VSUP > 9.0 V TJ = 150C, ILOAD = 50 mA; VSUP > 9.0 V(27) TJ = 150C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(27) Output Current Limitation(28) 0 V < VOUT < VSUP - 2.0 V Open Load Current Detection(29) Leakage Current -0.2 V < VHSX < VS2 + 0.2 V Short-circuit Detection Threshold(30) 5.5 V < VSUP < 27 V Over-temperature Shutdown(31), (32) Hysteresis(32) THSSD THSSD_HYS VTHSC VSUP -2.0 140 - - 160 10 - 180 - C C IOLHSX ILEAK - - 10 V ILIMHSX 60 - 90 5.0 250 7.5 mA A RDS(ON) - - - - - - 7.0 10 14 mA Symbol Min Typ Max Unit
Over-temperature Shutdown L1 INPUT PIN (L1) Low Detection Threshold(33) 5.5 V < VSUP < 27 V High Detection Threshold(33) 5.5 V < VSUP < 27 V Hysteresis(33) 5.5 V < VSUP < 27 V Input Current(34)
VTHL 2.0 VTHH 3.0 VHYS 0.4 IIN -10 RL1IN RATIOL1 0.95 3.42 VRATIOL1OFFSET
V 2.5 3.0 V 3.5 4.0 V 0.8 1.4 A - 1300 10 2000 k
-0.2 V < VIN < VS1 Analog Input Impedance(35) Analog Input Divider Ratio (RATIOL1 = VL1 / VADOUT0) L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 Analog Output offset Ratio L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 Analog Inputs Matching L1DS (L1 Divider Select) = 0 L1DS (L1 Divider Select) = 1 L1MATCHING
800
1.0 3.6
1.05 3.78 mV
-80 -22
6.0 2.0
80 22 %
96 96
100 100
104 104
Notes 27. This parameter is production tested up to TA = 125C, and guaranteed by process monitoring up to TJ = 150C. 28. 29. 30. 31. 32. 33. 34. 35. When over-current occurs, the corresponding high side stays ON with limited current capability and the HSxCL flag is set in the HSSR. When open load occurs, the flag (HSxOP) is set in the HSSR. HS automatically shutdown if HSOT occurs or if the HVSE flag is enabled and an over-voltage occurs. When over-temperature shutdown occurs, both high sides are turned off. All flags in HSSR are set. Guaranteed by characterization but not production tested If L1 pin is unused it must be connected to ground. Analog multiplexer input disconnected from L1 input pin. Analog multiplexer input connected to L1 input pin. 33910
Analog Integrated Circuit Device Data Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy)(37) ANALOG MULTIPLEXER Temperature Sense Analog Output Voltage TA = -40C TA = 25C TA = 125C Temperature Sense Analog Output Voltage per characterization TA = 25C Internal Chip Temperature Sense Gain Internal Chip Temperature Sense Gain per characterization at 3 temperatures(38) See Figure 16, Temperature Sense Gain VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0) 5.5 V < VSUP < 27 V VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(38) 5.5 _CZ (38) (36)
Symbol
Min
Typ
Max
Unit
REXT WDACC
20 -15
- -
200 15
k %
VADOUT0_TEMP 2.0 2.8 3.6 VADOUT0_25 3.1 3.15 3.0 2.8 3.6 4.6 3.2
V
V
STTOV STTOV_3T RATIOVSENSE
9.0 9.9
10.5 10.2
12 10.5
mV/K mV/K
5.0 RATIOVSENSECZ 5.15
5.25
5.5
5.25
5.35 mV
-10
30 mV
-30
-12.6
0
ANALOG OUTPUT (ADOUT0) Maximum Output Voltage -5.0 mA < IO < 5.0 mA Minimum Output Voltage -5.0 mA < IO < 5.0 mA RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD) Low-state Output Voltage IOUT = 1.5 mA High-state Output Voltage IOUT = -250 A Notes 36. For VSUP 4.7 to 18 V 37. 38. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in k) These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed by production test. VOH VDD -0.8 - VDD VOL 0.0 - 0.8 V V VOUT_MIN 0.0 - 0.35 VOUT_MAX VDD -0.35 - VDD V V
33910
12
Analog Integrated Circuit Device Data Freescale Semiconductor
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD) Low-state Input Voltage High-state Input Voltage Pin Pull-up Current, 0 V < VIN < 3.5 V VIL VIH IPUIN -0.3 0.7 x VDD 10 - - 20 0.3 x VDD VDD +0.3 30 V V A Symbol Min Typ Max Unit
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
LIN PHYSICAL LAYER WITH J2602 FEATURE ENABLED (BIT DIS_J2602 = 0) LIN Under Voltage threshold Positive and Negative threshold (VTHP, VTHN) Hysteresis (VTHP - VTHN) LIN PHYSICAL LAYER, TRANSCEIVER Operating Voltage Range Supply Voltage Range Voltage Range within which the device is not destroyed Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V Input Leakage Current at the receiver Driver off; VBUS = 0 V; VBAT = 12 V Leakage Output Current to GND Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS VBAT Control unit disconnected from ground(40) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V(41) Receiver Dominant State IBUSNO_BAT - VBUSDOM - Receiver Recessive State VBUSREC 0.6 Receiver Threshold Center (VTH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) Voltage Drop at the serial Diode in pull-up path VBAT_SHIFT GND_SHIFT Notes 39. Parameters guaranteed for 7.0 V VSUP 18 V. 40. 41. Loss of local ground must not affect communication in the residual network. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition. VSERDIODE VSHIFT_BAT VSHIFT_GND VHYS - 0.4 0 0 - 0.175 1.0 10% 10% V VBAT VBAT VBUS_CNT 0.475 0.5 0.525 VSUP - - VSUP - 0.4 VSUP - 100 VSUP IBUS_NO_GND -1.0 - 1.0 A IBUS_PAS_REC - - 20 mA IBUS_PAS_DOM -1.0 - - mA A (LIN)(39) VBAT VSUP VSUP_NON_OP IBUS_LIM 40 90 200 8.0 7.0 -0.3 18 18 40 V V V mA VTH_UNDER_
VOLTAGE
V 5.0 400 6.0 mV
VJ2602_DEG
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic LIN PHYSICAL LAYER, TRANSCEIVER (LIN) (CONTINUED) LIN Wake-up threshold from Stop or Sleep Mode(42) LIN Pull-up Resistor to VSUP Over-temperature Shutdown
(43) (39)
Symbol
Min
Typ
Max
Unit
VBUSWU RSLAVE TLINSD TLINSD_HYS 20 140 -
5.3 30 160 10
5.8 60 180 -
V k C C
Over-temperature Shutdown Hysteresis
Notes 42. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale does not guarantee this parameter during the product's life time. 43. When over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.
33910
14
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SPI INTERFACE TIMING (SEE Figure 13, PAGE 22) SPI Operating Frequency SCLK Clock Period SCLK Clock High Time(44) SCLK Clock Low Time(44) Falling Edge of CS to Rising Edge of SCLK(44) Falling Edge of SCLK to CS Rising Edge(44) MOSI to Falling Edge of SCLK(44) Falling Edge of SCLK to MOSI(44) MISO Rise Time(44) CL = 220 pF MISO Fall Time(44) CL = 220 pF Time from Falling or Rising Edges of - MISO Low-impedance - MISO High-impedance Time from Rising Edge of SCLK to MISO Data Valid(44) 0.2 x VDD MISO 0.8 x VDD, CL = 100 pF RST OUTPUT PIN Reset Low-level Duration After VDD High (see Figure 12, page 22) Reset Deglitch Filter Time WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) Watchdog Time Period(45) External Resistor REXT = 20 k (1%) External Resistor REXT = 200 k (1%) Without External Resistor REXT (WDCONF Pin Open) t PWD 8.5 79 110 10 94 150 11.5 108 205 ms t RST t RSTDF 0.65 350 1.0 480 1.35 900 ms ns
CS to:(44)
Symbol
Min
Typ
Max
Unit
f SPIOP tPSCLK tWSCLKH tWSCLKL tLEAD tLAG tSISU tSIH tRSO
- 250 110 110 100 100 40 40
- - - - - - - -
4.0 N/A N/A N/A N/A N/A N/A N/A
MHz ns ns ns ns ns ns ns ns
- tFSO -
40
- ns
40
- ns
tSOEN tSODIS tVALID
0.0 0.0
- -
50 50 ns
0.0
-
75
Notes 44. This parameter is guaranteed by process monitoring but not production tested. 45. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in k)
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic L1 INPUT L1 Filter Time Deglitcher(46) STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation(46) Normal Request Mode Timeout (see Figure 12, page 22) Cyclic Sense ON Time from Stop and Sleep Mode(47) Cyclic Sense Accuracy(46) Delay Between SPI Command and HS Turn On(48) 9.0 V < VSUP < 27 V Delay Between SPI Command and HS Turn Off(48) 9.0 V < VSUP < 27 V Delay Between Normal Request and Normal Mode After a Watchdog Trigger Command (Normal Request Mode)(46) Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and: Normal Request Mode, VDD ON and RST HIGH First Accepted SPI Command Minimum Time Between Rising and Falling Edge on the CS J2602 DEGLITCHER VSUP Deglitcher(49) (DIS_J2602 = 0) t S-OFF - - 10 s - - 15 -- -- 10 s 80 N/A -- s t S-ON - - 10 s t WUF 8.0 20 38 s Symbol Min Typ Max Unit
t STOP
- t NR TOUT TON 110 130 -35 - 150 200 5.0 205 270 +35
s ms s % s
t SNR2N
t WUCS t WUSPI t 2CS
9.0 90 4.0
tJ2602_DEG
35 50 70
s
Notes 46. This parameter is guaranteed by process monitoring but not production tested. 47. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale does not guarantee this parameter during the product's life time. 48. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load. 49. This parameter has not been monitoring during operating life test.
33910
16
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION(50), (51) Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 s, 7.0 V VSUP 18 V Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 s, 7.6 V VSUP 18 V -- -- 0.581 0.396 -- --
D1
D2
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION(50), (52) Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 s, 7.0 V VSUP 18 V Duty Cycle 4: THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 s, 7.6 V VSUP 18 V -- -- 0.590 0.417 -- --
D3
D4
Notes 50. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 6, page 20. 51. See Figure 7, page 20. 52. See Figure 8, page 20.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33910 and -40C TA 85C for the 34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS Propagation Delay and Symmetry(54) Propagation Delay of Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR Bus Wake-Up Deglitcher (Sleep and Stop Bus Wake-Up Event Reported From Sleep Mode
(57) (53)
SRFAST
--
20
--
V / s
s
t REC_PD t REC_SYM t PROPWL t WAKE_SLEEP t WAKE_STOP t TXDDOM
-- - 2.0 42
4.2 -- 70
6.0 2.0 95 s s
Modes)(55)(59) (56)
-- 9.0 0.65
-- 27 1.0
1500 35 1.35 s
From Stop Mode(58) TXD Permanent Dominant State Delay PULSE WIDTH MODULATION INPUT PIN (PWMIN) PWMIN pin(59) Max. frequency to drive HS output pins
fPWMIN 10
kHz
Notes 53. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 6, page 20. 54. See Figure 9, page 21 55. See Figure 10, page 21 for Sleep and Figure 11, page 21 for Stop Mode. 56. This parameter is tested on automatic tester but has not been monitoring during operating life test. 57. The measurement is done with 1.0 F capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V. See Figure 10, page 21. The delay depends of the load and capacitor on VDD. 58. 59. In Stop Mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11, page 21. This parameter is guaranteed by process monitoring but not production tested.
33910
18
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
33910
1.0 nF TRANSIENT PULSE GENERATOR
LIN
(NOTE)
GND
PGND LGND
AGND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 4. Test Circuit for Transient Test Pulses (LIN) 33910
1.0 nF L1 10 k PGND LGND AGND Transient Pulse Generator (Note) GND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.
Figure 5. Test Circuit for Transient Test Pulses (L1)
VSUP
R0 TXD RXD C0 LIN R0 AND C0 COMBINATIONS: * 1.0 K and 1.0 nF * 660 and 6.8 nF * 500 and 10 nF
Figure 6. Test Circuit for LIN Timing Measurements
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
19
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TXD tBIT tBIT
VLIN_REC
THREC(MAX) THDOM(MAX) 74.4% VSUP 58.1% VSUP
tBUS_DOM(MAX)
tBUS_REC(MIN) Thresholds of receiving node 1
LIN
THREC(MIN) THDOM(MIN) 42.2% VSUP 28.4% VSUP
Thresholds of receiving node 2
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD
Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1)
RXD
Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2)
Figure 7. LIN Timing Measurements for Normal Slew Rate
TXD tBIT tBIT
VLIN_REC
THREC(MAX) THDOM(MAX) 77.8% VSUP 61.6% VSUP
tBUS_DOM(MAX)
tBUS_REC(MIN) Thresholds of receiving node 1
LIN
THREC(MIN) THDOM(MIN) 38.9% VSUP 25.1% VSUP
Thresholds of receiving node 2
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD
Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1)
RXD
Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2)
Figure 8. LIN Timing Measurements for Slow Slew Rate
33910
20
Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
VLIN_REC VBUSREC VBUSDOM 0.6% VSUP 0.4% VSUP LIN BUS SIGNAL VSUP
RXD
tREC_PDF
tREC_PDR
Figure 9. LIN Receiver Timing
VLIN_REC
LIN
5.0 V DOMINANT LEVEL
VBUSWU
3.0 V VDD tPROPWL tWAKE_SLEEP
Figure 10. LIN Wake-Up Sleep Mode Timing
VLIN_REC
LIN
5.0 V
VBUSWU DOMINANT LEVEL
IRQ
tPROPWL
tWAKE_STOP
Figure 11. LIN Wake-up Stop Mode Timing
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
21
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
VSUP
VDD
RST
tRST
tNRTOUT
Figure 12. Power On Reset and Normal Request Timeout Timing
tPSCLK CS tLEAD SCLK tWSCLKL tSISU tSIH tWSCLKH tLAG
MOSI
UNDEFINED tVALID tSOEN
D0
DON'T CARE
D7
DON'T CARE
tSODIS
MISO
D0
DON'T CARE
D7
Figure 13. SPI Timing Characteristics
33910
22
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33910 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 33910 is well suited to perform keypad applications via the LIN bus. Power switches are provided on the device configured as high side outputs. Other ports are also provided, which include a Hall Sensor port supply, and one wake-up capable pin. An internal voltage regulator provides power to a MCU device. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground.
FUNCTIONAL PIN DESCRIPTION
See Figure 1, 33910 Simplified Application Diagram, page 1, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on page 4 for a description of the pin locations in the package.
MASTER OUT SLAVE IN PIN (MOSI)
The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the negative edge of SCLK.
MASTER IN SLAVE OUT PIN (MISO)
The MISO pin sends data to an SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this output pin changes on the positive edge of the SCLK. When CS is High, this pin will remain in the high-impedance state.
RECEIVER OUTPUT PIN (RXD)
The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD Low when LIN bus is dominant, RXD High when LIN bus is recessive.
TRANSMITTER INPUT PIN (TXD)
The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating.
CHIP SELECT PIN (CS)
CS is an active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in the same SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched. A valid transmission must consist of 8 bits only. While in STOP Mode, a low-to-high level transition on this pin will generate a wake-up condition for the 33910.
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN bus specification 2.0, 2.1, and SAE J2602-2. The LIN interface is only active during Normal Mode. See Table 7, Operating Modes Overview.
ANALOG MULTIPLEXER PIN (ADOUT0)
The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer, including the VSENSE and L1 input voltages, and the internal junction temperature.
SERIAL DATA CLOCK PIN (SCLK)
The SCLK pin is the SPI clock input. MISO data changes on the positive transition of the SCLK. MOSI is sampled on the negative edge of the SCLK.
PWM INPUT CONTROL PIN (PWMIN)
This digital input can control the high sides drivers in Normal Request and Normal Mode. To enable PWM control, the MCU must perform a write operation to the High Side Control Register (HSCR). This pin has an internal 20 A current pull-up.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
RESET PIN (RST)
This bidirectional pin is used to reset the MCU in case the 33910 detects a reset condition, or to inform the 33910 that the MCU has just been reset. After release of the RST pin, Normal Request Mode is entered. The RST pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure which allows this pin to be shorted either to VDD or to GND during software development, without the risk of destroying the driver.
INTERRUPT PIN (IRQ)
The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request Mode or to signal a wake-up from Stop Mode. This active low output will transition to high only after the interrupt is acknowledged by a SPI read of the respective status bits.
WATCHDOG CONFIGURATION PIN (WDCONF)
The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window watchdog period. When connected directly to ground, the watchdog will be disabled. When this pin is left open, the watchdog period is fixed to its lower precision internal default value (150 ms typical).
input for the analog multiplexer. When used to sense voltage outside the module, a 33 kohm series resistor must be used on the input. When used as wake-up input L1 can be configured to operate in cyclic-sense mode. In this mode one or both of the high side switches are configured to be periodically turned on and sample the wake-up input. If a state change is detected between two cycles a wake-up is initiated. The 33910 can also wake-up from Stop or Sleep by a simple state change on L1. When used as analog input, the voltage present on the L1 pin is scaled down by an selectable internal voltage divider and can be routed to the ADOUT0 output through the analog multiplexer. Note: If L1 input is selected in the analog multiplexer, it will be disabled as digital input and remains disabled in low power mode. No wake-up feature is available in that condition. When the L1 input is not selected in the analog multiplexer, the voltage divider is disconnected from that input.
HIGH SIDE OUTPUT PINS (HS1 AND HS2)
These two high side switches are able to drive loads such as relays or lamps. Their structures are connected to the VS2 supply pin. The pins are short-circuit protected and both outputs are also protected against overheating. HS1 and HS2 are controlled by SPI and can respond to a signal applied to the PWMIN input pin. HS1 and HS2 outputs can also be used during low-power mode for the cyclic-sense of the wake inputs.
GROUND CONNECTION PINS (AGND, PGND, LGND)
The AGND, PGND and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator module. The PGND and LGND pins are used for high current load return as in the LIN interface pin. Note: PGND, AGND and LGND pins must be connected together.
POWER SUPPLY PINS (VS1 AND VS2)
Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection and negative transient voltages with external components. These pins sustain standard automotive voltage conditions such as a load dump at 40 V. The high side switches (HS1 and HS2) are supplied by the VS2 pin. All other internal blocks are supplied by the VS1 pin.
DIGITAL/ANALOG PIN (L1)
The L1 pin is multi purpose input. It can be used as a digital input, which can be sampled by reading the SPI and used for wake-up when 33910 is in low power mode or used as analog
33910
24
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
VOLTAGE SENSE PIN (VSENSE)
This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery voltage. The ESD structure on this pin allows for excursion up to +40 V and down to -27 V, allowing this pin to be connected directly to the battery line. It is strongly recommended to connect a 10 kohm resistor in series with this pin for protection purposes.
The HVDD pin needs to be connected to an external capacitor to stabilize the regulated output voltage.
+5V MAIN REGULATOR OUTPUT PIN (VDD)
An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply a microcontroller. The pin is current limited against shorts to GND and over-temperature protected. During Stop Mode, the voltage regulator does not operate with its full drive capabilities and the output current is limited. During Sleep Mode, the regulator output is completely shut down.
HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)
This pin provides a switchable supply for external hall sensors. While in Normal Mode, this current limited output can be controlled through the SPI.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES INTRODUCTION
The 33910 offers three main operating modes: Normal (Run), Stop, and Sleep (Low Power). In Normal Mode, the device is active and is operating under normal application conditions. The Stop and Sleep Modes are low power modes with wake-up capabilities. In Stop Mode, the voltage regulator still supplies the MCU with VDD (limited current capability), while in Sleep Mode the voltage regulator is turned off (VDD = 0 V). Wake-up from Stop Mode is initiated by a wake-up interrupt. Wake-up from Sleep Mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the Mode Control Register (MCR). Figure 14 describes how transitions are done between the different operating modes. Table 7, 28, gives an overview of the operating modes. The VDD regulator is ON and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog function will be enabled. The wake-up input (L1) can be read as digital input or have its voltage routed through the analog-multiplexer. The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0, 2.1 and SAEJ2602. The LIN bus can transmit and receive information. The high side switches are active and have PWM capability according to the SPI configuration. The interrupts are generated to report failures for VSUP over/under-voltage, thermal shutdown, or thermal shutdown prewarning on the main regulator.
SLEEP MODE
The Sleep Mode is a low power mode. From Normal Mode, the device enters into Sleep Mode by sending one SPI command through the Mode Control Register (MCR), or (VDD low > 150 ms) with VSUV = 0. When in Reset Mode, a VDD under-voltage condition with no VSUP under-voltage (VSUV = 0) will send the device to Sleep Mode. All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up input with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. The internal low-power oscillator may be active if the IC is configured for cyclic-sense. In this condition, one of the high side switches is turned on periodically and the wake-up input is sampled. Wake-up from Sleep Mode is similar to a power-up. The device goes in Reset Mode except that the SPI will report the wake-up source and the BATFAIL flag is not set.
RESET MODE
The 33910 enters the Reset Mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, it enters the Normal Request Mode and the RST pin is driven high. The Reset Mode is entered if a reset condition occurs (VDD low, watchdog trigger fail, after wake-up from Sleep Mode, Normal Request Mode timeout occurs).
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the device after the Reset Mode, or after a wake-up from Stop Mode. In Normal Request Mode, the VDD regulator is ON, the RESET pin is High, and the LIN is operating in RX Only Mode. As soon as the device enters in the Normal Request Mode an internal timer is started for 150 ms (typical value). During these 150 ms, the MCU must configure the Timing Control Register (TIMCR) and the Mode Control Register (MCR) with MOD2 and MOD1 bits set = 0, to enter the Normal Mode. If within the 150 ms timeout, the MCU does not command the 33910 to Normal Mode, it will enter in Reset Mode. If the WDCONF pin is grounded in order to disable the watchdog function, it goes directly in Normal Mode after the Reset Mode.
STOP MODE
The Stop Mode is the second low power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The application MCU is always supplied while the 33910 is operating in Stop Mode. The device can enter into Stop Mode only by sending the SPI command. When the application is in this mode, it can wake-up from the 33910 side (for example: cyclic sense, force wake-up, LIN bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop Mode will transition the 33910 to Normal Request Mode and generates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin.
NORMAL MODE
In Normal Mode, all 33910 functions are active and can be controlled by the SPI interface and the PWMIN pin.
33910
26
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
Normal Request Timeout Expired(NRTOUT) ) Normal Request timeout expired (t NRTOUT VDD Low VDD Low VDD High and
Power Down
Power Up
Reset
Reset Delay (t RST) Expired VDD High and Reset Delay (tRST) expired
Normal Request
WDdisabled WD Disabled WD Trigger WD trigger
VDDLow Low V
DD
WD Failed WD failed
Normal
Stop Command STOP Command
VDDLow (>NRTOUT) expired) Expired VDD LOW (>t NRTOUT and VSUV = 0 and VSUV = 0
Sleep Command SLEEP Command
Wake-up (Reset) Wake-Up (Reset)
Sleep
Stop
VDD Low VDD Low
Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF pin connected to GND) WD - means Watchdog WD Trigger: Watchdog is triggered by SPI command WD Failed:WD disabled - trigger or trigger occurs in closed window No watchdog means Watchdog disabled (WDCONF terminal connected to GND) WD trigger command sent via is triggered by SPI command Stop Command: Stop - means Watchdog SPI WD failed - means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command - means STOP LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up. Wake-up from Stop Mode: L1 state change, command sent via SPI SLEEP Command state change, LIN bus wake-up, via SPI Wake-up from Sleep Mode: L1 - means SLEEP command send Periodic wake-up. Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge
Figure 14. Operating Modes and Transitions
Wake-upInterrupt Wake-Up (Interrupt)
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
Table 7. Operating Modes Overview
Function VDD HVDD HSx Analog Mux L1 LIN Watchdog Voltage Monitoring Notes 60. 61. 62. 63. 64. Reset Mode Normal Request Mode Full VSUP/VDD Full SPI(60) SPI/PWM(61) SPI Input Rx-Only 150 ms (typ.) timeout VSUP/VDD Normal Mode Full SPI SPI/PWM SPI Input Stop Mode Stop Note(62) Wake-up Sleep Mode Note(63) Wake-up Wake-up -
Full/Rx-Only Rx-Only/Wake-up On
(64)
/Off
VDD
VSUP/VDD
Operation can be enabled/controlled by the SPI. Operation can be controlled by the PWMIN input. HSx switches can be configured for cyclic sense operation in Stop Mode. HSx switches can be configured for cyclic sense operation in Sleep Mode. Windowing operation when enabled by an external resistor.
INTERRUPTS
Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. The interrupts which can be generated, change according to the operating mode. While in Normal and Normal Request Modes, the 33910 signals through interrupts special conditions which may require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the Interrupt Source Register (ISR). While in Stop Mode, interrupts are used to signal wake-up events. Sleep Mode does not use interrupts. Wake-up is performed by powering-up the MCU. In Normal and Normal Request Mode the wake-up source can be read by SPI. The interrupts are signaled to the MCU by a low logic level of the IRQ pin, which will remain low until the interrupt is acknowledged by a SPI read command of the ISR register. The IRQ pin will then be driven high. Interrupts are only asserted while in Normal, Normal Request and Stop Mode. Interrupts are not generated while the RST pin is low. The following is a list of the interrupt sources in Normal and Normal Request Modes. Some of these can be masked by writing to the SPI - Interrupt Mask Register (IMR).
Low-voltage Interrupt: Signals when the supply line (VS1) voltage drops below the VSUV threshold (VSUV). High-voltage Interrupt: Signals when the supply line (VS1) voltage increases above the VSOV threshold (VSOV). Over-temperature Prewarning: Signals when the 33910 temperature has reached the preshutdown warning threshold. It is used to warn the MCU that an over-temperature shutdown in the main 5.0 V regulator is imminent. LIN Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit: These signal fault conditions within the LIN interface will cause the LIN driver to be disabled. In order to restart the operation, the fault must be removed and TXD must go recessive. High Side Over-temperature Shutdown: Signals a shutdown in the high side outputs.
33910
28
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
RESET
To reset a MCU the 33910 drives the RST pin low for the time the reset condition lasts. After the reset source is removed, the state machine will drive the RST output low for at least 1.0 ms (typical value) before driving it high. In the 33910, four main reset sources exist: 5.0 V Regulator Low-voltage-Reset (VRSTTH) The 5.0 V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects that the voltage at the VDD pin has dropped below the reset threshold VRSTTH the 33910 will issue a reset. In case of overtemperature, the voltage regulator will be disabled and the voltage monitoring will issue a VDDOT Flag independently of the VDD voltage. Window Watchdog Overflow If the watchdog counter is not properly serviced while its window is open, the 33910 will detect an MCU software runaway and will reset the microcontroller. Wake-up From Sleep Mode During Sleep Mode, the 5V regulator is not active, hence all wake-up requests from Sleep Mode require a power-up/ reset sequence. External Reset The 33910 has a bidirectional reset pin which drives the device to a safe state (same as Reset Mode) for as long as this pin is held low. The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality is also active in Stop Mode. After the RST pin is released, there is no extra t RST to be considered.
In order to select and activate direct wake-up from L1 input, the Wake-up Control Register (WUCR) must be configured with appropriate L1WE input enabled or disabled. The wake-up input's state is read through the Wake-up Status Register (WUSR). L1 input is also used to perform cyclic-sense wake-up. Note: Selecting an L1 input in the analog multiplexer before entering low power mode will disable the wake-up capability of the L1 input Wake-up from Wake-up input (L1) with cyclic sense timer enabled The SBCLIN can wake-up at the end of a cyclic sense period if on the wake-up input line (L1) a state change occurs. One or both HSx switch can be activated in Sleep or Stop Modes from an internal timer. Cyclic sense and force wakeup are exclusive. If cyclic sense is enabled, the force wakeup can not be enabled. In order to select and activate the cyclic sense wake-up from the L1 input, before entering in low power modes (Stop or Sleep Modes), the following SPI set-up has to be performed: In WUCR: select the L1 input to WU-enable. In HSCR: enable the desired HSx. * In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits. * Perform Goto Sleep/Stop command. Forced Wake-up The 33910 can wake-up automatically after a predetermined time spent in Sleep or Stop Mode. Cyclic sense and Forced wake-up are exclusive. If Forced wake-up is enabled, the Cyclic Sense can not be enabled. To determine the wake-up period, the following SPI set-up has to be sent before entering in low power modes: * In TIMCR: select the CS/WD bit and determine the low power mode period with CYSTx bits. * In HSCR: all HSx bits must be disabled. CS Wake-up While in Stop Mode, a rising edge on the CS will cause a wake-up. The CS wake-up does not generate an interrupt, and is not reported on SPI. LIN Wake-up While in the low-power mode, the 33910 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by a dominant to recessive transition will cause a LIN wake-up. This behavior protects the system from a short to ground bus condition. The bit RXONLY = 1 from LINCR Register disables the LIN wake-up from Stop Mode.
WAKE-UP CAPABILITIES
Once entered into one of the low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal Mode operation. In Stop Mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep Mode the wake-up is performed by activating the 5.0 V regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers and reading the Interrupt Source Register. There is no specific SPI register bit to signal a CS wake-up or external reset. If necessary this condition is detected by excluding all other possible wake-up sources. Wake-up from Wake-up input (L1) with cyclic sense disabled The wake-up line is dedicated to sense state changes of external switch and wake-up the MCU (in Sleep or Stop Mode).
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
RST Wake-up While in Stop Mode, the 33910 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, the 33910 will change to Normal Request or Normal Modes depending on the WDCONF pin configuration. The RST wake-up does not generate an interrupt and is not reported via SPI. From Stop Mode, the following wake-up events can be configured: * Wake-up from L1 input without cyclic sense * Cyclic sense wake-up inputs * Force wake-up * CS wake-up * LIN wake-up * RST wake-up From Sleep Mode, the following wake-up events can be configured: * Wake-up from L1 input without cyclic sense * Cyclic sense wake-up inputs * Force wake-up * LIN wake-up
WINDOW CLOSED NO WATCHDOG CLEAR ALLOWED WINDOW OPEN FOR WATCHDOG CLEAR
WD TIMING X 50%
WD TIMING X 50%
WD PERIOD (tPWD) WD TIMING SELECTED BY RESISTOR ON WDCONF PIN
WINDOW WATCHDOG
The 33910 includes a configurable window watchdog which is active in Normal Mode. The watchdog can be configured by an external resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears are performed by writing through the SPI in the MOD bits of the Mode Control Register (MCR). During the first half of the SPI timeout, watchdog clears are not allowed, but after the first half of the SPI timeout window, the clear operation opens. If a clear operation is performed outside the window, the 33910 will reset the MCU, in the same way as when the watchdog overflows.
Figure 15. Window Watchdog Operation To disable the watchdog function in Normal Mode the user must connect the WDCONF pin to ground. This measure effectively disables Normal Request Mode. The WDOFF bit in the Watchdog Status Register (WDSR) will be set. This condition is only detected during Reset Mode. If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms (typ.) and signals the faulty condition through the Watchdog Status Register (WDSR). The watchdog timebase can be further divided by a prescaler which can be configured by the Timing Control Register (TIMCR). During Normal Request Mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request Mode. In case of a timeout, the 33910 will enter into Reset Mode, resetting the microcontroller before entering again into Normal Request Mode.
FAULTS DETECTION MANAGEMENT
The 33910 has the capability to detect faults like an over or under-voltage on VS1, TxD in permanent Dominant State, Over-temperature on HS, LIN. It is able to take corrective actions accordingly. Most of faults are monitoring through SPI and the Interrupt pin. The microcontroller can also take actions. The following table summarizes all fault sources the device is able to detect with associated conditions. The status for a device recovery and the SPI or pins monitoring are also described.
33910
30
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
Table 8. Fault Detection Management Conditions
MONITORING(66) BLOCK FAULT MODE CONDITION FALLOUT RECOVERY REG (FLAG, BIT)
VSR (BATFAIL, 0)
INTERRUPT
IRQ low + ISR (0101)
(67)
BATTERY FAIL
All modes
VSUP<3.0 V (typ) then power-up
In Normal mode, HS shutdown if bit HVSE=1 (reg MCR) Reset (65)
Condition gone Condition gone, to re-enable HS write to HSCR registers
VSUP OVERVOLTAGE VSUP UNDERVOLTAGE VDD UNDERVOLTAGE VDD OVER-TEMP PREWARNING VDD OVERTEMPERATURE RXD PIN SHORT CIRCUIT TXD PIN PERMANENT DOMINANT LIN DRIVER OVERTEMPERATURE HIGH SIDE DRIVERS OVERTEMPERATURE HS1 OPEN-LOAD DETECTION High Side HS2 OPEN-LOAD DETECTION HS1 OVERCURRENT HS2 OVERCURRENT
VSUP > 19.25 V (typ) Normal, Normal Request VSUP < 6.0 V (typ)
VSR (VSOV,3)
VSR (VSUV,2)
Power Supply
IRQ low + ISR (0101) IRQ low + ISR (0101) -
All except Sleep
VDD < 4.5 V (typ) Temperature > 115C (typ) Temperature > 170C (typ) RXD pin shorted to GND or 5 V
Condition gone VSR (VDDOT,1)
All except Low Power modes
VDD shutdown, Reset then Sleep LIN trans shutdown LIN transmitter reenabled once the condition is gone and TXD is high
LINSR, (RXSHORT,3)
LIN
Normal, Normal Request
TXD pin low for more than 1s (typ) Temperature > 160C (typ) Temperature > 160C (typ)
LINSR (TXDOM,2)
LIN transmitter shutdown
IRQ low + ISR (0100)(67)
LINSR (LINOT,1) Condition gone, to re-enable HS write to HSCR reg
Both HS thermal shutdown
All flags in HSSR are set
IRQ low + ISR (0010) (67)
HSSR (HS1OP,1) Normal, Normal Request Current through HSx < 5.0 mA (typ) HSSR (HS2OP,3) Condition gone Current through HSx tends to rise above the current limit 60 mA (min) The MCU did not command the device to Normal mode within the 150 ms timeout after reset WD timeout or WD clear within the window closed WDCONF pin is floating HSx on with limited current capability 60 mA (min) HSSR (HS1CL,0) -
HSSR (HS2CL,2)
NORMAL REQUEST TIME-OUT EXPIRED
Normal Request
Reset -
-
Watchdog
WATCHDOG TIMEOUT
Reset WDSR (WDTO, 3)
Normal
WATCHDOG ERROR
Normal
WD internal lower precision timebase 150 ms (typ)
Connect WDCONF to a resistor or to GND
WDSR (WDERR, 2)
Notes 65. 66. 67.
When in Reset mode a VDD under-voltage condition combined with no VSUP under-voltage (VSUV=0) will send the device to Sleep mode. Registers to be read when back in Normal Request or Normal Mode depending on the fault. Interrupts only generated in Normal, Normal Request and Stop modes Unless masked, If masked IRQ remains high and the ISR flags are not set.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
TEMPERATURE SENSE GAIN
The analog multiplexer can be configured via SPI to allow the ADOUT0 pin to deliver the internal junction temperature of the device.
The graph below illustrates the internal chip temp sense obtained per characterization at 3 temperatures with 3 different lots and 30 samples.
Temperature Sense Analog Output Voltage 5 4.5 4 Vadout0 (V)
3.5 3
2.5 2 -50 0 50 Temperature (C)
Figure 16. Temperature Sense Gain
100
150
HIGH SIDE OUTPUT PINS HS1 AND HS2
These outputs are two high side drivers intended to drive small resistive loads or LEDs incorporating the following features: * PWM capability (software maskable) * Open load detection * Current limitation * Over-temperature shutdown (with maskable interrupt) * High-voltage shutdown (software maskable) * Cyclic sense
The high side switches are controlled by the bits HS1:2 in the High Side Control Register (HSCR). PWM Capability (direct access) Each high side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the bits HS1 and PWMHS1 are set in the High Side Control Register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low. This applies to HS2 configuring HS2 and PWMHS2 bits.
33910
32
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
HVSE
Interrupt Control Module
High Voltage Shutdown High-Side Interrupt
VDD VDD
PWMIN
PWMHSx
VS2
MOD1:2
on/off
High Side Driver
charge pump open load detection current limitation over-temperture shutdown (interrupt maskable) high voltage shutdown (maskable) HSx
HSx
Control
HSxOP HSxCL
Status
Wakeup Module
Cyclic Sense
Figure 17. High Side Drivers HS1 and HS2 Open Load Detection Each high side driver signals an open load condition if the current through the high side is below the open load current threshold. The open load condition is indicated with the bits HS1OP and HS2OP in the High Side Status Register (HSSR). Current Limitation Each high side driver has an output current limitation. In combination with the over-temperature shutdown the highside drivers are protected against over-current and shortcircuit failures. When the driver operates in the current limitation area, it is indicated with the bits HS1CL and HS2CL in the HSSR. Note: If the driver is operating in current limitation mode, excessive power might be dissipated. Over-temperature Protection (HS Interrupt) Both high side drivers are protected against overtemperature. In case of an over-temperature condition both high side drivers are shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source Register (ISR). A thermal shutdown of the high side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. If the bit HSM is set in the Interrupt Mask Register (IMR), then an interrupt (IRQ) is generated. A write to the High Side Control Register (HSCR), when the over-temperature condition is gone, will re-enable the high side drivers. High-voltage Shutdown In case of a high voltage condition and if the high voltage shutdown is enabled (bit HVSE in the Mode Control Register (MCR) is set both high side drivers are shut down. A write to the High Side Control Register (HSCR), when the high voltage condition is gone, will re-enable the high side drivers. Sleep And Stop Mode The high side drivers can be enabled to operate in Sleep and Stop Mode for cyclic sensing. Also see Table 7, Operating Modes Overview.
LIN PHYSICAL LAYER
The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification and has the following features: * LIN physical layer 2.0, 2.1 and SAEJ2602 compliant * Slew rate selection * Over-temperature shutdown * Advanced diagnostics The LIN driver is a low side MOSFET with thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed.
LIN Pin The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance.
WAKE-UP MODULE
LIN Wake-up
MOD1:2 LSR0:1 VS1 J2602 RXONLY RXSHORT TXDOM LINOT
LIN DRIVER
Slope and Slew Rate Control Over-temperature Shutdown (interrupt maskable)
30 K LIN TXD SLOPE CONTROL WAKE-UP FILTER RXD RECEIVER LGND
Figure 18. LIN Interface Slew Rate Selection The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the bits LSR1:0 in the LIN Control Register (LINCR). The initial slew rate is optimized for 20 kBit/s. J2602 Conformance To be compliant with the SAE J2602-2 specification, the J2602 feature has to be enabled in the LINCR Register (bit DIS_J2602 sets to 0). The LIN transmitter is disabled in case of a VSUP under-voltage condition occurs and TXD is in Recessive State: the LIN bus goes in Recessive State and RXD goes high. The LIN transmitter is not disabled if TXD is in Dominant State. A deglitcher on VSUP (tJ2602_DEG) is implemented to avoid false switching. If the (DIS_J2602) bit is set to 1, the J2602 feature is disabled and the communication TXD-LIN-RXD works for
33910
VSUP down to 4.6 V (typical value) and then the communication is interrupted. The (DIS_J2602) bit is set per default to 0. Over-temperature Shutdown (LIN Interrupt) The output low side FET is protected against overtemperature conditions. In case of an over-temperature condition, the transmitter will be shut down and the LINOT bit in the LIN Status Register (LINSR) is set. If the LINM bit is set in the Interrupt Mask Register (IMR), an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. RXD Short-circuit Detection (LIN Interrupt) The LIN transceiver has a short-circuit detection for the RXD output pin. If the device transmits and in case of a shortcircuit condition, either 5.0 V or Ground, the RXSHORT bit in
34
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES
the LIN Status Register (LINSR) is set and the transmitter is shut down. If the LINM bit is set in the Interrupt Mask Register (IMR), an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone (transition on RXD) and TXD is high. A read of the LIN Status Register (LINSR) without the RXD pin short-circuit condition will clear the bit RXSHORT. TXD Dominant Detection (LIN Interrupt) The LIN transceiver monitors the TXD input pin to detect a stuck in dominant (0 V) condition. In case of a stuck condition (TXD pin 0 V for more than 1 second (typ.)), the transmitter is shut down and the TXDOM bit in the LIN Status Register (LINSR) is set. If the LINM bit is set in the IMR, an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once TXD is high. A read of the LIN Status Register (LINSR) with the TXD pin at 5.0 V will clear the bit TXDOM.
LIN Receiver Operation Only While in Normal Mode, the activation of the RXONLY bit disables the LIN TXD driver. In case of a LIN error condition, this bit is automatically set. If Stop mode is selected with this bit set, the LIN wake-up functionality is disabled and the RXD pin will reflect the state of the LIN bus. STOP Mode And Wake-up Feature During Stop Mode operation, the transmitter of the physical layer is disabled. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than TPROPWL followed by a rising edge will generate a wake-up interrupt, and will be reported in the Interrupt Source Register (ISR). Also see Figure 11, page 21. SLEEP Mode And Wake-up Feature During Sleep Mode operation, the transmitter of the physical layer is disabled. The receiver must be active to detect wake-up events on the LIN bus line. A dominant level longer than TPROPWL followed by a rising edge will generate a system wake-up (Reset), and will be reported in the Interrupt Source Register (ISR). Also see Figure 10, page 21.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS 33910 SPI INTERFACE AND CONFIGURATION
The serial peripheral interface creates the communication link between a microcontroller (master) and the 33910. The interface consists of four pins (see Figure 19): * CS -- Chip Select * MOSI -- Master-out Slave-in * MISO -- Master-in Slave-out * SCLK-- Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0) and the slave replies with 4 system status bits (VMS,LINS,HSS,n.d.) + 4 bits of status information (S3:S0).
CS
Register Write Data MOSI A3 A2 A1 A0 C3 C2 C1 C0
Register Read Data MISO VMS LINS HSS S3 S2 S1 S0
SCLK Read Data Latch Write Data Latch
Rising: 33910 changes MISO/ MCU changes MOSI
Falling: 33910 samples MOSI/ MCU samples MISO
Figure 19. SPI Protocol During the inactive phase of the CS (HIGH), the new data The rising edge of the Chip Select CS indicates the end of transfer is prepared. the transfer and latches the write data (MOSI) into the register. The CS high forces MISO to the high-impedance The falling edge of the CS indicates the start of a new data state. transfer and puts the MISO in the low-impedance state and Register reset values are described along with the reset latches the analog status data (Register read data). condition. Reset condition is the condition causing the bit to With the rising edge of the SPI clock (SCLK), the data is be set to its reset value. The main reset conditions are: moved to MISO/MOSI pins. With the falling edge of the SPI - Power-On Reset (POR): the level at which the logic is clock (SCLK), the data is sampled by the receiver. reset and BATFAIL flag sets. The data transfer is only valid if exactly 8 sample clock - Reset Mode edges are present during the active (low) phase of CS. - Reset done by the RST pin (ext_reset)
33910
36
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
SPI REGISTER OVERVIEW
Table 9. System Status Register
BIT Adress(A3:A0) $0 - $F Register Name / Read / Write Information 7 SYSSR - System Status Register R VMS 6 LINS 5 HSS 4 -
Table 10 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R. Table 10. SPI Register Overview
BIT Adress(A3:A0) Register Name / Read / Write Information 3 MCR - Mode Control Register $0 VSR - Voltage Status Register $1 $2 WUSR - Wake-up Status Register $3 $4 LINSR - LIN Status Register $5 $6 HSSR - High Side Status Register $7 HSSR - High Side Status Register TIMCR - Timing Control Register $A WDSR - Watchdog Status Register $B $C $D $E ISR - Interrupt Source Register $F ISR - Interrupt Source Register R R ISR3 ISR3 ISR2 ISR2 ISR1 ISR1 ISR0 ISR0 WDSR - Watchdog Status Register AMUXCR - Analog Multiplexer Control Register CFR - Configuration Register IMR - Interrupt Mask Register R R W W W WDTO WDTO L1DS HVDD HSM R R W HS2OP HS2OP CS/WD CYST2 WDERR WDERR MX2 CYSX8 0 CYST1 WDOFF WDOFF MX1 0 LINM CYST0 WDWO WDWO MX0 0 VMM HS2CL HS2CL WD2 HS1OP HS1OP WD1 HS1CL HS1CL WD0 LINSR - LIN Status Register HSCR - High Side Control Register R R W RXSHORT RXSHORT PWMHS2 TXDOM TXDOM PWMHS1 LINOT LINOT HS2 0 0 HS1 WUSR - Wake-up Status Register LINCR - LIN Control Register R R W DIS_J2602 RXONLY LSR1 L1 L1 LSR0 VSR - Voltage Status Register WUCR - Wake-up Control Register R R W VSOV VSOV 0 VSUV VSUV 0 VDDOT VDDOT 0 BATFAIL BATFAIL L1WE W HVSE 2 0 1 MOD2 0 MOD1
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
REGISTER DEFINITIONS
System Status Register - SYSSR The System Status Register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It summarizes the status of the Voltage Monitor Status (VMS), LIN Status (LINS) and High Side Status (HSS). Table 11. System Status Register
S7
Read VMS
HS1CL HS1OP HS2CL HS2OP HSS
Figure 22. High Side Status Mode Control Register - MCR
S6
LINS
S5
HSS
S4
-
The Mode Control Register (MCR) allows switching between the operation modes and to configure the 33910. Writing the MCR will return the VSR. Table 12. Mode Control Register - $0
C3
Write Reset Value Reset Condition HVSE 1
VMS - Voltage Monitor Status This read-only bit indicates that one or more bits in the VSR are set. 1 = Voltage Monitor bit set 0 = None
C2
0 0
C1
MOD2 -
C0
MOD1 -
POR
POR
-
-
BATFAIL VDDOT VSUV VSOV Figure 20. Voltage Monitor Status LINS - LIN Status This read-only bit indicates that one or more bits in the LINSR are set. 1 = LIN Status bit set 0 = None VMS
HVSE - High-Voltage Shutdown Enable This write-only bit enables/disables automatic shutdown of the high side drivers during a high-voltage VSOV condition. 1 = automatic shutdown enabled 0 = automatic shutdown disabled MOD2, MOD1 - Mode Control Bits These write-only bits select the operating mode and allow clearing the watchdog in accordance with Table 10 Mode Control Bits. Table 13. Mode Control Bits
MOD2 MOD1 0 1 0 1 Description Normal Mode Stop Mode Sleep Mode Normal Mode + Watchdog Clear 0
LINOT TXDOM RXSHORT Figure 21. LIN Status HSS - High Side Switch Status This read-only bit indicates that one or more bits in the HSSR are set. 1 = High Side Status bit set 0 = None LINS
0 1 1
Voltage Status Register - VSR Returns the status of the several voltage monitors. This register is also returned when writing to the Mode Control Register (MCR). Table 14. Voltage Status Register - $0/$1
S3
Read VSOV
S2
VSUV
S1
VDDOT
S0
BATFAIL
33910
38
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
VSOV - VSUP Over-voltage This read-only bit indicates an over-voltage condition on the VS1 pin. 1 = Over-voltage condition. 0 = Normal condition. VSUV - VSUP Under-voltage This read-only bit indicates an under-voltage condition on the VS1 pin. 1 = Under-voltage condition. 0 = Normal condition. VDDOT - Main Voltage Regulator Over-temperature Warning This read-only bit indicates that the main voltage regulator temperature reached the Over-temperature Prewarning Threshold. 1 = Over-temperature Prewarning 0 = Normal BATFAIL - Battery Fail Flag. This read-only bit is set during power-up and indicates that the 33910 had a Power-On-Reset (POR). Any access to the MCR or VSR will clear the BATFAIL flag. 1 = POR Reset has occurred 0 = POR Reset has not occurred Wake-Up Control Register - WUCR This register is used to control the digital wake-up input. Writing the WUCR will return the Wake-Up Status Register (WUSR).
Table 15. Wake-Up Control Register - $2
C3
Write Reset Value Reset Condition 0 1
C2
0 1
C1
0 1
C0
L1WE 1
POR, Reset Mode or ext_reset
L1WE - Wake-up Input Enable This write-only bit enables/disables the L1 input. In Stop and Sleep Mode the L1WE bit activates the L1 input for wakeup. If the L1 input is selected on the analog multiplexer, the L1WE is masked to 0. 1 = Wake-up Input enabled. 0 = Wake-up Input disabled. Wake-up Status Register - WUSR This register is used to monitor the digital wake-up input and is also returned when writing to the WUCR. Table 16. Wake-up Status Register - $2/$3
S3
Read -
S2
-
S1
-
S0
L1
L1 - Wake-up input 1 This read-only bit indicates the status of the L1 input. If the L1 input is not enabled, then the Wake-up status will return 0. After a wake-up from Stop or Sleep Mode this bit also allows to verify the L1 input has caused the wake-up, by first reading the Interrupt Status Register (ISR) and then reading the WUSR. The source of the wake-up is only reported on the first WUCR or WUSR access. 1 = L1 pin high, or L1 is the source of the wake-up. 0 = L1 pin low, disabled or selected as an analog input.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
39
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
LIN Control Register - LINCR This register controls the LIN physical interface block. Writing the LIN Control Register (LINCR) returns the LIN Status Register (LINSR). Table 17. LIN Control Register - $4
C3
Write Reset Value DIS_J2602 0
Table 18. LIN Slew Rate Control
LSR1 0 0 1 LSR0 0 1 0 1 Description Normal Slew Rate (up to 20 kb/s) Slow Slew Rate (up to 10 kb/s) Fast Slew Rate (up to 100 kb/s) Reserved
C2
RXONLY 0 POR, Reset Mode, ext_reset or LIN failure gone*
C1
LSR1 0
C0
LSR0
1
LIN Status Register - LINSR
0
This register returns the status of the LIN physical interface block and is also returned when writing to the LINCR. Table 19. LIN Status Register - $4/$5
S3 S2
TXDOM
Reset Condition
POR
POR
S1
LINOT
S0
0
* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag resets automatically when the failure is gone.
Read
RXSHORT
J2602 - LIN Dominant Voltage Select This write-only bit controls the J2602 circuitry. If the circuitry is enabled (bit sets to 0), the TXD-LIN-RXD communication works down to the battery under-voltage condition is detected. Below, the bus is in recessive state. If the circuitry is disabled (bit sets to 1), the communication TXD-LIN-RXD works down to 4.6 V (typical value). 0 = Enabled J2602 feature. 1 = Disabled J2602 feature. RXONLY - LIN Receiver Operation Only This write-only bit controls the behavior of the LIN transmitter. In Normal Mode, the activation of the RXONLY bit disables the LIN transmitter. In case of a LIN error condition, this bit is automatically set. In Stop Mode this bit disables the LIN wake-up functionality, and the RXD pin will reflect the state of the LIN bus. 1 = only LIN receiver active (Normal Mode) or LIN wakeup disabled (Stop Mode). 0 = LIN fully enabled. LSRx - LIN Slew-Rate This write-only bit controls the LIN driver slew-rate in accordance with Table 18.
RXSHORT - RXD Pin Short-circuit This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The shortcircuit delay must be a worst case of 8.0 s to be detected and to shut down the driver. To clear this bit, it must be read after the condition is gone (transition detected on RXD pin). The LIN driver is automatically re-enabled once the condition is gone and TXD is high. 1 = RXD short-circuit condition. 0 = None. TXDOM - TXD Permanent Dominant This read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LIN transmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second (typical value). To clear this bit, it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes High. 1 = TXD stuck at dominant fault detected. 0 = None. LINOT - LIN Driver Over-temperature This read-only bit signals that the LIN transceiver was shutdown due to over-temperature. The transmitter is automatically re-enabled after the over-temperature condition is gone and TXD is high. The LINOT bit is cleared after SPI read once the condition is gone. 1 = LIN over-temperature shutdown 0 = None
33910
40
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
High Side Control Register - HSCR This register controls the operation of the high side drivers. Writing to this register returns the High Side Status Register (HSSR). Table 20. High Side Control Register - $6
C3
Write Reset Value Reset Condition PWMHS2 0
Timing Control Register - TIMCR This register allows to configure the watchdog, the cyclic sense and Forced Wake-up periods. Writing to the Timing Control Register (TIMCR) will also return the Watchdog Status Register (WDSR). Table 22. Timing Control Register - $A
C3 C2
WD2
C2
PWMHS1 0
C1
HS2 0
C0
HS1
C1
WD1 CYST1 0
C0
WD0 CYST0 0
0
Write
CS/WD CYST2
POR
POR, Reset Mode, ext_reset, HSx over-temp or (VSOV & HVSE)
Reset Value Reset Condition
-
0
PWMHSx - PWM Input Control Enable. This write-only bit enables/disables the PWMIN input pin to control the respective high side switch. The corresponding high side switch must be enabled (HSx bit). 1 = PWMIN input controls HSx output. 0 = HSx is controlled only by SPI. HSx - HSx Switch Control. This write-only bit enables/disables the corresponding high side switch. 1 = HSx switch on. 0 = HSx switch off. High Side Status Register - HSSR This register returns the status of the high side switches and is also returned when writing to the HSCR. Table 21. High Side Status Register - $6/$7
S3
Read HS2OP
-
POR
CS/WD - Cyclic Sense or Watchdog prescaler select This write-only bit selects which prescaler is being written to, the Cyclic Sense/Forced Wake-up prescaler or the Watchdog prescaler. 1 = Cyclic Sense/Forced Wake-up Prescaler selected 0 = Watchdog Prescaler select WDx - Watchdog Prescaler This write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table . This configuration is valid only if windowing watchdog is active. Table 23. Watchdog Prescaler
WD2 0 WD1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 Prescaler Divider 1 2 4 6 8 10 12 14
S2
HS2CL
S1
HS1OP
S0
HS1CL
0 0 0
High Side thermal shutdown A thermal shutdown of the high side drivers is indicated by setting all HSxOP and HSxCL bits simultaneously. HSxOP - High Side Switch Open-Load Detection This read-only bit signals that the high side switches are conducting current below a certain threshold indicating possible load disconnection. 1 = HSx Open Load detected (or thermal shutdown) 0 = Normal HSxCL - High Side Current Limitation This read-only bit indicates that the respective high side switch is operating in current limitation mode. 1 = HSx in current limitation (or thermal shutdown) 0 = Normal
1 1 1 1
CYSTx - Cyclic Sense Period Prescaler Select This write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the Configuration Register (CFR) (see page 43). This option is only active if one of the high side switches is enabled when entering in Stop or Sleep Mode. Otherwise, a timed wake-up is performed after the period shown in Table . Table 24. Cyclic Sense and Force Wake-up Interval
CYSX8(68) X CYST2 0 CYST1 0 CYST0 0 Interval No cyclic sense(69)
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
41
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
Table 24. Cyclic Sense and Force Wake-up Interval
CYSX8 0 0 0 0 0 0 0 1 1 1 1 1 1 1
(68)
CYST2 0 0 0 1 1 1 1 0 0 0 1 1 1 1
CYST1 0 1 1 0 0 1 1 0 1 1 0 0 1 1
CYST0 1 0 1 0 1 0 1 1 0 1 0 1 0 1
Interval 20 ms 40 ms 60 ms 80 ms 100 ms 120 ms 140 ms 160 ms 320 ms 480 ms 640 ms 800 ms 960 ms 1120 ms
timeouts are disabled and the device automatically enters Normal Mode out of Reset. This might be necessary for software debugging and for programming the Flash memory. 1 = Watchdog is disabled 0 = Watchdog is enabled WDWO - Watchdog Window Open This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case WDERR is High. 1 = Watchdog window open 0 = Watchdog window closed Analog Multiplexer Control Register - MUXCR This register controls the analog multiplexer and selects the divider ration for the L1 input divider. Table 26. Analog Multiplexer Control Register -$C
C3
Write Reset Value Reset Condition L1DS 1
Notes 68. bit CYSX8 is located in Configuration Register (CFR) 69. No Cyclic Sense and no Force Wake-up available.
C2
MX2 0
C1
MX1 0
C0
MX0 0
Watchdog Status Register - WDSR This register returns the Watchdog status information and is also returned when writing to the TIMCR. Table 25. Watchdog Status Register - $A/$B
S3
Read WDTO
POR
POR, Reset Mode or ext_reset
L1DS - L1 Analog Input Divider Select This write-only bit selects the resistor divider for the L1 analog input. Voltage is internally clamped to VDD. 0 = L1 Analog divider: 1 1 = L1 Analog divider: 3.6 (typ.) MXx - Analog Multiplexer Input Select These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table . When disabled or when in Stop or Sleep Mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption. Table 27. Analog Multiplexer Channel Select
MX2 0 0 0 0 1 1 MX1 0 0 1 1 0 0 1 1 MX0 0 1 0 1 0 1 0 1 Meaning Disabled Reserved Die Temperature Sensor VSENSE input L1 input Reserved Reserved Reserved
S2
WDERR
S1
WDOFF
S0
WDWO
WDTO - Watchdog Timeout This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the Watchdog within the window closed. Any access to this register or the Timing Control Register (TIMCR) will clear the WDTO bit. 1 = Last reset caused by watchdog timeout 0 = None WDERR - Watchdog Error This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision timebase. The Windowing function is disabled. 1 = WDCONF pin resistor missing 0 = WDCONF pin resistor not floating WDOFF - Watchdog Off This read-only bit signals that the watchdog pin connected to Ground and therefore disabled. In this case watchdog
1 1
33910
42
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
Configuration Register - CFR This register controls the Hall Sensor Supply enable/ disable and the cyclic sense timing multiplier. Table 28. Configuration Register - $D
C3
Write Reset Value Reset Condition HVDD 0 POR, Reset Mode or ext_reset
HSM - High Side Interrupt Mask This write-only bit enables/disables interrupts generated in the high side block. 1 = HS Interrupts Enabled 0 = HS Interrupts Disabled LINM - LIN Interrupts Mask
C2
CYSX8 0
C1
0 0
C0
0 0
This write-only bit enables/disables interrupts generated in the LIN block. 1 = LIN Interrupts Enabled 0 = LIN Interrupts Disabled VMM - Voltage Monitor Interrupt Mask This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor Block is the VSUP over-voltage interrupt. 1 = Interrupts Enabled 0 = Interrupts Disabled Interrupt Source Register - ISR This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ will be driven high for 10s and then be driven low again. This register is also returned when writing to the Interrupt Mask Register (IMR). Table 30. Interrupt Source Register - $E/$F
S3
Read ISR3
POR
POR
POR
HVDD - Hall Sensor Supply Enable This write-only bit enables/disables the state of the hall sensor supply. 1 = HVDD on 0 = HVDD off CYSX8 - Cyclic Sense Timing x 8. This write-only bit influences the cyclic sense and Forced Wake-up period as shown in Table . 1 = Multiplier enabled 0 = None Interrupt Mask Register - IMR This register allows masking of some of the interrupt sources. No interrupt will be generated to the MCU and no flag will be set in the ISR register. The 5.0V Regulator overtemperature prewarning interrupt and Under-voltage (VSUV) interrupts can not be masked and will always cause an interrupt. Writing to the IMR will return the ISR. Table 29. Interrupt Mask Register - $E
C3
Write Reset Value Reset Condition HSM 1
S2
ISR2
S1
ISR1
S0
ISR0
ISRx - Interrupt Source Register
C2
0 1
C1
LINM 1
C0
VMM 1
These read-only bits indicate the interrupt source following Table . If no interrupt is pending then all bits are 0. In case more than one interrupt is pending, the interrupt sources are handled sequentially multiplex.
POR
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
43
FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS
Table 31. Interrupt Sources
Interrupt Source ISR3 ISR2 ISR1 ISR0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 none maskable no interrupt L1 Wake-up from Stop and Sleep Mode LIN Wake-up Voltage Monitor Interrupt (Low Voltage and VDD over-temperature) Forced Wake-up maskable no interrupt HS Interrupt (Over-temperature) Reserved LIN Interrupt (RXSHORT, TXDOM, LIN OT) Voltage Monitor Interrupt (High Voltage) lowest none highest Priority
33910
44
Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATION
TYPICAL APPLICATION
The 33910 can be configured in several applications. The figure below shows the 33910 in the typical Slave Node Application.
V D1
BAT
VS1
VS2
C2
C1
VDD Internal Bus
IRQ C4 C3
Interrupt Control Module LVI, HVI, HTI, OCI
Voltage Regulator
C5
AGND
5V Output Module
HVDD
Hall Sensor Supply
VDD RST IRQ
Reset Control Module LVR, HVR, HTR, WD,
RST TIMER PWMIN
Window Watchdog Module High Side Control Module
R1 HS1
MISO MOSI SPI SCLK CS
SPI & CONTROL
HS2
Chip Temp Sense Module
Analog Multiplexer
VBAT Sense Module
VSENSE
MCU
R2 L1
Analog Input Module
A/D
ADOUT0
Wake Up Module
Digital Input Module
RXD SCI TXD C6
LIN Physical Layer
LIN
LIN
A/D
WDCONF R7
PGND
AGND
LGND
Typical Component Values: C1 = 47 F; C2 = C4 = 100 nF; C3 = 10 F; C5 = 220 pF R1 = 10 k; R2 = 20 k-200 k Recommended Configuration of the not Connected Pins (NC): Pin 15, 16, 17, 19, 20, 21, 22 = GND Pin 11 = open (floating) Pin 28 = this pin is not internally connected and may be used for PCB routing optimization.
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
45
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under Available Documentation column select Packaging Information.
AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D
33910
46
Analog Integrated Circuit Device Data Freescale Semiconductor
IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACKAGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTATION,
PACKAGE DIMENSIONS (Continued)
AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D
33910
Analog Integrated Circuit Device Data Freescale Semiconductor
47
REVISION HISTORY
REVISION HISTORY
Revision 1.0 2.0
Date 5/2007 9/2007
Description of Changes * * * * * * * * * * * Initial Release Several textual corrections Page 11: "Analog Output offset Ratio" changed to "Analog Output offset" +/-22mV Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5 Page 12: Common mode input impedance corrected to 75k Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release Revision number incremented at engineering request. Changed Functional Block Diagram on page 24. Datasheet updated according to the Pass1.2 silicon version electrical parameters Add Maximum Rating on IBUS_NO_GND parameter Added L1, Temperature Sense Analog Output Voltage per characterization(38), Internal Chip Temperature Sense Gain per characterization at 3 temperatures(38) See Figure 16, Temperature Sense Gain, VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(38), and VSENSE Output Related Offset per characterization(38) parameters Added Temperature Sense Gain section Minor corrections to ESD Capability, (20), Cyclic Sense ON Time from Stop and Sleep Mode(47), Lin Bus Pin (LIN), Serial Data Clock Pin (SCLK), Master Out Slave In Pin (MOSI), Master In Slave Out Pin (MISO), Digital/analog Pin (L1), Normal Request Mode, Sleep Mode, LIN Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit:, Fault Detection Management Conditions, Lin Physical Layer, LIN Interface, Over-temperature Shutdown (LIN Interrupt), LIN Receiver Operation Only, SPI Protocol, L1 - Wake-up input 1, LIN Control Register - LINCR, and RXSHORT - RXD Pin Short-circuit Updated Freescale form and style
3.0 4.0 5.0
9/2007 2/2008 11/2008
* *
*
33910
48
Analog Integrated Circuit Device Data Freescale Semiconductor
How to Reach Us:
Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
MC33910 Rev. 5.0 12/2008

▲Up To Search▲

Price & Availability of MC33910

	To Download MC33910 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .